1. Field of the Invention
This invention relates to integrated logic circuits and more particularly, to a method and circuit for checking integrated circuit chips.
2. Description of Prior Art
Redundant checking systems are well known in prior art. For example, in the past, two identical logic circuits have been wired in parallel, the same input information being supplied to each, with the output of each circuit being compared in a comparison checking circuit for equality. For example, two identical computers have been operated side-by-side with the same problem being supplied to each. A comparison of the results from each computer at some point in the computation indicates whether one of the computers has malfunctioned.
Because of the high cost of duplicating logic in the past, this type of redundancy checking has been mainly limited to military applications or applications in the space program wherein back-up computers are necessary.
Checking using redundant logic is an attractive technique and it is desirable to have some inexpensive way of checking duplicate circuits without requiring expensive error-checking circuitry. It is particularly desirable to extend the principle of redundant logic checking to modern integrated circuit technology wherein the circuits being so complex, it is becoming increasingly difficult to check their operation.
It is, therefore, a principal object of the present invention to provide an inexpensive redundant logic checking method particularly suited to integrated circuit technology.
It is a further object of this invention to provide an error-checking circuit for use with integrated circuit chips which does not require an additional part number or chip for the error-checking function.
Briefly, the method of checking integrated circuit chips, in accordance with the present invention, is as follows:
An error-checking logic circuit is fabricated on each of a number of chips. Data from data processing logic on each chip is outputted via a first path to one input of its respective error circuit. The data is also outputted via a second path to an output pin or pins on the chip. The inputs of the chips are externally wired in parallel, and since the chips receive the same input data, they should each generate the same output at any instant of time. The second path to the output pin or pins of all but one of said chips is inhibited by energizing a check input of a pin dedicated to this purpose, so that its output data does not reach its output pin or pins. The output pin or pins of the chip is connected internally via a third path to the other input of the error circuit. In this manner data generated internally on all but one of the chips via the first path is checked against data generated and passed externally from the other chip via the third path. The error-checking circuit on the chip which has its outputs enabled compares its internal data against the data present on the output pin or pins, thereby checking its own output drivers.
The invention has the advantage that when operating properly, both chips should be in exactly the same state throughout all time and therefore the outputs should agree.
In accordance with an aspect of the invention, three-state drivers may be provided such that the output drivers of the chip(s) activated to be a checker (or multiple checkers) are put into a high-impedance state so that no off-chip outputs are generated.